VHDLVisualizer

VHDLVisualizer is a tool able to visualize a schematics of the structural VHDL model, simulate this model, and visualize the simulation results in the visualized structure. It is intended for education and for the structural models at gate level of abstraction.

Binaries: VHDLVisualizer v7

Useful tools:

GHDL simulator webpage

GTKWave waveform viewer

Note: Path to the tools has to be without spaces!

Publications:

• Dominik Macko and Katarína Jelemenská, "HDL Model Verification Based on Visualization and Simulation," in Proceedings of World Congress on Engineering 2012, 2012, pp. 1095-1100. download
• Dominik Macko and Katarína Jelemenská, "VHDLVisualizer: HDL Model Visualization with Simulation-Based Verification," in Proceedings of the 2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2012, pp. 199-200. DOI: 10.1109/DDECS.2012.6219056
• Dominik Macko, Katarína Jelemenská, and Pavel Čičák, "HDL model simulation-based verification in a VHDLVisualizer visualization environment," in AWERProcedia Information Technology and Computer Science: 2nd World Conference on Information Technology (WCIT 2011), vol. 1 (2012), 2012, pp. 1431-1436. download
• Dominik Macko and Katarína Jelemenská, "VHDL Structural Model Visualization," in 2011 IEEE EUROCON - International Conference on Computer as a Tool (EUROCON), 2011. DOI: 10.1109/EUROCON.2011.5929348